1. Field of the Invention
This invention relates to a semiconductor device including a groove interconnecting element, such as Dual Damascene structure, and a manufacturing method of the semiconductor device.
2. Background Art
In the manufacturing process of a semiconductor device, recently, the Dual Damascene fabrication technology is widely adopted in order to form multilayer interconnections in the device. FIGS. 9A to 9E are explanatory views showing one example of fabrication processes of multilayer interconnections by the Dual Damascene fabrication technology. First, lower interconnections 93 made of copper etc. are formed on the surface of a semiconductor wafer W (indicated with “Si-sub” in FIGS. 9A to 9E). Next, as a first insulation film 94, a silicon oxide film (SiO2-film) is formed so as to cover the lower interconnections 93 on the wafer W. Further, as a first intermediate film 95, a silicon nitride film (SiN-film) is formed on the first insulation film 94 and subjected to patterning. In the patterning of the first intermediate film 95, an opening 95a narrower than the width of the lower interconnection 93 is formed in an area where a via-hole 99a is formed subsequently and where a groove interconnection using the via-hole 99a is connected to the lower interconnection 93 (see FIG. 9A).
Next, a SiO2-film as a second insulation film 96 is formed on the first intermediate film 95. This second insulation film 96 is formed so that the opening 95a is embedded by silicon oxide (SiO2) (see FIG. 9B). Subsequently, as a second intermediate film 97, a silicon nitride film (SiN-film) is formed on the second insulation film 96 and thereafter, a photo-resist film 98 is formed on the second intermediate film 97. Then, by photo lithography technology, openings are formed in the photo-resist film 98. In succession, by etching the second intermediate film 97 while masking the photo-resist film 98, openings 97a are formed in the second intermediate film 97 (see FIG. 9C).
After removing the photo-resist film 98, the first insulation film 94 and the second insulation film 96 are etched while utilizing the second intermediate film 97 as an etching mask and also utilizing the first intermediate film 95 as an etching stopper layer (FIG. 9D). Consequently, the via-hole 99a and a trench 99b are formed in the first insulation film 94 and the second insulation film 96 (see Japanese Patent Publication No. 2001-60582, 3rd. paragraph to 6th. paragraph).
In case of the dual damascene method mentioned above, however, the first intermediate film 95 formed between the first insulation film 94 and the second insulation film 96 in order to form the via-hole 99a has a dielectric constant higher than respective dielectric constants of the first insulation film 94 and the second insulation film 96, causing a problem in the advance of development of semiconductor devices, such as LSI (Large Scale Integrated circuit) of recent years. For instance, in the development of semiconductor devices of recent years, there has been developed an interlayer insulation film of low dielectric, namely, low-k film (or low-εfilm) as the first insulation film 94 and the second insulation film 96, in view of speeding-up, low consumption of power, etc. of the semiconductor device. In the method shown in FIGS. 9A to 9E, however, there is a problem that the first intermediate film 95 increases the dielectric constant of the whole insulating layers (lamination of the first insulation film 94, the first intermediate film 95 and the second insulating film 96).
In order to solve the above-mentioned problem, there is known a fabrication process of multilayer interconnection by the dual damascene method shown in FIGS. 10A to 10C. According to the method of FIGS. 10A to 10C, it is firstly performed to form an insulation film 82 on a wafer W having a lower interconnection 81 formed thereon and subsequently, a via-hole 82a is formed in the insulation film 82 (see FIG. 10A). Next, an intermediate film 83, such as antireflection film, is formed on the insulation film 82. Next, a photo-resist film 84 is formed on the intermediate film and thereafter, it is performed to expose and develop the photo-resist film 84 in the patterning process (see FIG. 10B). In succession, the wafer W is etched with use of the photo-resist film 84 as an etching stopper layer. Consequently, both upper portions of the intermediate film 83 and the insulation film 82 are etched, so that a trench 82b is formed in communication with the via-hole 82a (see FIG. 10C).
Although this application of the dual damascene method of FIGS. 10A to 10C has an advantage of avoiding the increase in dielectric constant of the insulation film 82 (in case of low-k film) because of no formation of an intermediate film in the insulation film 82, there is a possibility that when etching the wafer W in order to form the trench 82b, its bottom surface 85 is coarsened disadvantageously, requiring a new process to smooth such a roughness on the bottom surface 85.